
Computer Organization and Architecture : Designing for Performance
by Stallings, William-
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Summary
Author Biography
Table of Contents
Web Site | p. vi |
Preface | p. ix |
Overview | p. 1 |
Introduction | p. 3 |
Organization and Architecture | p. 5 |
Structure and Function | p. 6 |
Outline of the Book | p. 12 |
Internet and Web Resources | p. 15 |
Computer Evolution and Performance | p. 17 |
A Brief History of Computers | p. 19 |
Designing for Performance | p. 39 |
Pentium and PowerPC Evolution | p. 43 |
Recommended Reading and Web Sites | p. 46 |
Problems | p. 47 |
The Computer System | p. 49 |
System Buses | p. 51 |
Computer Components | p. 53 |
Computer Function | p. 56 |
Interconnection Structures | p. 69 |
Bus Interconnection | p. 71 |
PCI | p. 80 |
Recommended Reading and Web Sites | p. 89 |
Problems | p. 90 |
Timing Diagrams | p. 92 |
Internal Memory | p. 95 |
Computer Memory System Overview | p. 97 |
Semiconductor Main Memory | p. 103 |
Cache Memory | p. 117 |
Pentium II and PowerPC Cache Organizations | p. 132 |
Advanced DRAM Organization | p. 137 |
Recommended Reading and Web Sites | p. 142 |
Problems | p. 143 |
Performance Characteristics of Two-Level Memories | p. 145 |
External Memory | p. 153 |
Magnetic Disk | p. 155 |
RAID | p. 163 |
Optical Memory | p. 172 |
Magnetic Tape | p. 177 |
Recommended Reading and Web Sites | p. 178 |
Problems | p. 179 |
Input/Output | p. 181 |
External Devices | p. 184 |
I/O Modules | p. 188 |
Programmed I/O | p. 191 |
Interrupt-Driven I/O | p. 195 |
Direct Memory Access | p. 203 |
I/O Channels and Processors | p. 207 |
The External Interface: SCSI and FireWire | p. 209 |
Recommended Reading and Web Sites | p. 223 |
Problems | p. 224 |
Operating System Support | p. 227 |
Operating System Overview | p. 229 |
Scheduling | p. 241 |
Memory Management | p. 247 |
Pentium II and PowerPC Memory Management | p. 259 |
Recommended Reading and Web Sites | p. 268 |
Problems | p. 269 |
The Central Processing Unit | p. 271 |
Computer Arithmetic | p. 273 |
The Arithmetic and Logic Unit (ALU) | p. 275 |
Integer Representation | p. 276 |
Integer Arithmetic | p. 282 |
Floating-Point Representation | p. 298 |
Floating-Point Arithmetic | p. 305 |
Recommended Reading and Web Sites | p. 314 |
Problems | p. 315 |
Number Systems | p. 317 |
Instruction Sets: Characteristics and Functions | p. 323 |
Machine Instruction Characteristics | p. 325 |
Types of Operands | p. 331 |
Pentium II and PowerPC Data Types | p. 333 |
Types of Operations | p. 336 |
Pentium II and PowerPC Operation Types | p. 349 |
Assembly Language | p. 358 |
Recommended Reading | p. 360 |
Problems | p. 360 |
Stacks | p. 364 |
Little-, Big-, and Bi-Endian | p. 368 |
Instruction Sets: Addressing Modes and Formats | p. 373 |
Addressing | p. 375 |
Pentium and PowerPC Addressing Modes | p. 382 |
Instruction Formats | p. 388 |
Pentium and PowerPC Instruction Formats | p. 397 |
Recommended Reading | p. 402 |
Problems | p. 402 |
CPU Structure and Function | p. 405 |
Processor Organization | p. 407 |
Register Organization | p. 409 |
The Instruction Cycle | p. 414 |
Instruction Pipelining | p. 419 |
The Pentium Processor | p. 434 |
The PowerPC Processor | p. 443 |
Recommended Reading | p. 450 |
Problems | p. 451 |
Reduced Instruction Set Computers | p. 455 |
Instruction Execution Characteristics | p. 458 |
The Use of a Large Register File | p. 462 |
Compiler-Based Register Optimization | p. 467 |
Reduced Instruction Set Architecture | p. 469 |
RISC Pipelining | p. 476 |
MIPS R4000 | p. 480 |
SPARC | p. 488 |
The RISC versus CISC Controversy | p. 494 |
Recommended Reading | p. 495 |
Problems | p. 496 |
Instruction-Level Parallelism and Superscalar Processors | p. 499 |
Overview | p. 501 |
Design Issues | p. 506 |
Pentium II | p. 515 |
PowerPC | p. 521 |
MIPS R10000 | p. 529 |
UltraSPARC-II | p. 531 |
IA-64/Merced | p. 534 |
Recommended Reading | p. 545 |
Problems | p. 546 |
The Control Unit | p. 551 |
Control Unit Operation | p. 553 |
Micro-operations | p. 555 |
Control of the Processor | p. 561 |
Hardwired Implementation | p. 573 |
Recommended Reading | p. 575 |
Problems | p. 576 |
Microprogrammed Control | p. 577 |
Basic Concepts | p. 579 |
Microinstruction Sequencing | p. 588 |
Microinstruction Execution | p. 593 |
TI 8800 | p. 605 |
Applications of Microprogramming | p. 615 |
Recommended Reading | p. 616 |
Problems | p. 617 |
Parallel Organization | p. 619 |
Parallel Processing | p. 621 |
Multiple Processor Organizations | p. 623 |
Symmetric Multiprocessors | p. 625 |
Cache Coherence and the MESI Protocol | p. 635 |
Clusters | p. 642 |
Nonuniform Memory Access | p. 646 |
Vector Computation | p. 650 |
Recommended Reading | p. 663 |
Problems | p. 664 |
Digital Logic | p. 669 |
Boolean Algebra | p. 670 |
Gates | p. 672 |
Combinational Circuits | p. 675 |
Sequential Circuits | p. 696 |
Problems | p. 707 |
Projects for Teaching Computer Organization and Architecture | p. 709 |
Research Projects | p. 710 |
Simulation Projects | p. 710 |
Reading/Report Assignments | p. 712 |
Glossary | p. 713 |
References | p. 725 |
Index | p. 739 |
Table of Contents provided by Syndetics. All Rights Reserved. |
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