Structure at a Glance |
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vi | |
Preface |
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xv | |
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PART 1 BACKGROUND AND MOTIVATION |
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1 | (80) |
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Combinational Digital Circuits |
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3 | (18) |
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Signals, Logic Operators, and Gates |
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3 | (4) |
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Boolean Functions and Expressions |
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7 | (1) |
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8 | (3) |
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Useful Combinational Parts |
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11 | (2) |
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Programmable Combinational Parts |
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13 | (2) |
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Timing and Circuit Considerations |
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15 | (6) |
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17 | (2) |
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References and Further Readings |
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19 | (2) |
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Digital Circuits with Memory |
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21 | (17) |
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Latches, Flip-Flops, and Registers |
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21 | (3) |
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24 | (1) |
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Designing Sequential Circuits |
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25 | (3) |
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28 | (2) |
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Programmable Sequential Parts |
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30 | (2) |
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Clocks and Timing of Events |
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32 | (6) |
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34 | (3) |
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References and Further Readings |
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37 | (1) |
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Computer System Technology |
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38 | (21) |
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From Components to Applications |
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39 | (2) |
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Computer Systems and Their Parts |
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41 | (4) |
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45 | (3) |
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Processor and Memory Technologies |
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48 | (3) |
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Peripherals, I/O, and Communications |
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51 | (3) |
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Software Systems and Applications |
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54 | (5) |
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56 | (2) |
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References and Further Readings |
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58 | (1) |
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59 | (22) |
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Cost, Performance, and Cost/Performance |
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59 | (3) |
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Defining Computer Performance |
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62 | (3) |
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Performance Enhancement and Amdahl's Law |
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65 | (2) |
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Performance Measurement vs Modeling |
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67 | (5) |
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Reporting Computer Performance |
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72 | (2) |
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The Quest for Higher Performance |
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74 | (7) |
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76 | (3) |
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References and Further Readings |
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79 | (2) |
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PART 2 INSTRUCTION-SET ARCHITECTURE |
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81 | (76) |
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Instructions and Addressing |
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83 | (20) |
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Abstract View of Hardware |
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83 | (3) |
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86 | (3) |
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Simple Arithmetic and Logic Instructions |
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89 | (2) |
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Load and Store Instructions |
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91 | (2) |
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Jump and Branch Instructions |
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93 | (4) |
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97 | (6) |
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99 | (3) |
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References and Further Readings |
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102 | (1) |
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103 | (20) |
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103 | (3) |
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Using the Stack for Data Storage |
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106 | (2) |
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108 | (2) |
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110 | (3) |
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113 | (3) |
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116 | (7) |
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120 | (2) |
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References and Further Readings |
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122 | (1) |
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Assembly Language Programs |
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123 | (16) |
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Machine and Assembly Languages |
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123 | (3) |
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126 | (1) |
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127 | (3) |
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130 | (1) |
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131 | (2) |
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Running Assembler Programs |
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133 | (6) |
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136 | (2) |
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References and Further Readings |
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138 | (1) |
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Instruction-Set Variations |
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139 | (18) |
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139 | (2) |
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Alternative Addressing Modes |
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141 | (4) |
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Variations in Instruction Formats |
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145 | (2) |
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Instruction-Set Design and Evolution |
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147 | (1) |
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148 | (3) |
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151 | (6) |
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154 | (2) |
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References and Further Readings |
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156 | (1) |
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PART 3 THE ARITHMETIC/LOGIC UNIT |
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157 | (84) |
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159 | (19) |
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Positional Number Systems |
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159 | (3) |
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162 | (3) |
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165 | (1) |
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166 | (3) |
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169 | (2) |
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171 | (7) |
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174 | (2) |
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References and Further Readings |
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176 | (2) |
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178 | (19) |
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178 | (2) |
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Carry Propagation Networks |
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180 | (3) |
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Counting and Incrementation |
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183 | (2) |
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185 | (3) |
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Logic and Shift Operations |
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188 | (3) |
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191 | (6) |
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193 | (3) |
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References and Further Readings |
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196 | (1) |
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197 | (22) |
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197 | (4) |
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201 | (3) |
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Programmed Multiplication |
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204 | (2) |
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206 | (4) |
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210 | (3) |
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213 | (6) |
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215 | (3) |
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References and Further Readings |
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218 | (1) |
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Floating-Point Arithmetic |
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219 | (22) |
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219 | (5) |
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Special Values and Exceptions |
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224 | (2) |
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226 | (3) |
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Other Floating-Point Operations |
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229 | (1) |
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Floating-Point Instructions |
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230 | (3) |
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Result Precision and Errors |
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233 | (8) |
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237 | (2) |
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References and Further Readings |
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239 | (2) |
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PART 4 DATA PATH AND CONTROL |
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241 | (74) |
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Instruction Execution Steps |
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243 | (15) |
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A Small Set of Instructions |
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244 | (2) |
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The Instruction Execution Unit |
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246 | (1) |
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247 | (2) |
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249 | (1) |
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Deriving the Control Signals |
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250 | (3) |
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Performance of the Single-Cycle Design |
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253 | (5) |
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255 | (2) |
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References and Further Readings |
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257 | (1) |
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258 | (19) |
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A Multicycle Implementation |
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258 | (3) |
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Clock Cycle and Control Signals |
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261 | (3) |
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The Control State Machine |
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264 | (2) |
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Performance of the Multicycle Design |
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266 | (1) |
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267 | (4) |
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271 | (6) |
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273 | (3) |
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References and Further Readings |
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276 | (1) |
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277 | (20) |
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277 | (4) |
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Pipeline Stalls or Bubbles |
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281 | (3) |
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Pipeline Timing and Performance |
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284 | (2) |
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Pipelined Data Path Design |
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286 | (3) |
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289 | (2) |
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291 | (6) |
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293 | (3) |
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References and Further Readings |
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296 | (1) |
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Pipeline Performance Limits |
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297 | (18) |
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Data Dependencies and Hazards |
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297 | (3) |
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300 | (2) |
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302 | (2) |
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304 | (2) |
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306 | (3) |
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309 | (6) |
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310 | (3) |
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References and Further Readings |
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313 | (2) |
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PART 5 MEMORY SYSTEM DESIGN |
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315 | (76) |
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317 | (18) |
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Memory Structure and SRAM |
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317 | (3) |
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320 | (3) |
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323 | (2) |
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Pipelined and Interleaved Memory |
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325 | (2) |
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327 | (2) |
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The Need for a Memory Hierarchy |
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329 | (6) |
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331 | (3) |
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References and Further Readings |
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334 | (1) |
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Cache Memory Organization |
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335 | (18) |
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335 | (3) |
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338 | (3) |
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341 | (1) |
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342 | (3) |
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345 | (1) |
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Improving Cache Performance |
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346 | (7) |
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348 | (4) |
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References and Further Readings |
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352 | (1) |
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353 | (18) |
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353 | (3) |
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356 | (3) |
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359 | (1) |
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360 | (1) |
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361 | (4) |
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Other Types of Mass Memory |
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365 | (6) |
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367 | (3) |
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References and Further Readings |
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370 | (1) |
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Virtual Memory and Paging |
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371 | (20) |
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The Need for Virtual Memory |
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371 | (2) |
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Address Translation in Virtual Memory |
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373 | (3) |
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Translation Lookaside Buffer |
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376 | (3) |
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Page Replacement Policies |
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379 | (3) |
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382 | (1) |
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Improving Virtual Memory Performance |
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383 | (8) |
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386 | (3) |
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References and Further Readings |
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389 | (2) |
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PART 6 INPUT/OUTPUT AND INTERFACING |
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391 | (74) |
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393 | (18) |
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Input/Output Devices and Controllers |
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393 | (2) |
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395 | (2) |
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397 | (3) |
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Hard-Copy Input/Output Devices |
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400 | (4) |
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Other Input/Output Devices |
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404 | (2) |
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Networking of Input/Output Devices |
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406 | (5) |
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408 | (2) |
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References and Further Readings |
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410 | (1) |
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411 | (18) |
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I/O Performance and Benchmarks |
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411 | (2) |
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413 | (3) |
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416 | (1) |
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Demand-Based I/O: Interrupts |
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417 | (1) |
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I/O Data Transfer and DMA |
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418 | (3) |
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Improving I/O Performance |
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421 | (8) |
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425 | (3) |
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References and Further Readings |
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428 | (1) |
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Buses, Links, and Interfacing |
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429 | (20) |
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Intra-and Intersystem Links |
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429 | (4) |
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433 | (2) |
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Bus Communication Protocols |
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435 | (3) |
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Bus Arbitration and Performance |
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438 | (2) |
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440 | (1) |
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441 | (8) |
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445 | (2) |
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References and Further Readings |
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447 | (2) |
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Context Switching and Interrupts |
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449 | (16) |
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449 | (2) |
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Interrupts, Exceptions, and Traps |
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451 | (2) |
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Simple Interrupt Handling |
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453 | (3) |
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456 | (2) |
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Types of Context Switching |
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458 | (2) |
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Threads and Multithreading |
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460 | (5) |
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462 | (2) |
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References and Further Readings |
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464 | (1) |
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PART 7 ADVANCED ARCHITECTURES |
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465 | (83) |
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Road to Higher Performance |
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467 | (23) |
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Past and Current Performance Trends |
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467 | (3) |
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Performance-Driven ISA Extensions |
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470 | (3) |
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Instruction-Level Parallelism |
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473 | (3) |
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Speculation and Value Prediction |
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476 | (3) |
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Special-Purpose Hardware Accelerators |
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479 | (3) |
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Vector, Array, and Parallel Processing |
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482 | (8) |
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485 | (3) |
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References and Further Readings |
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488 | (2) |
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Vector and Array Processing |
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490 | (18) |
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491 | (2) |
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Vector Processor Implementation |
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493 | (4) |
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Vector Processor Performance |
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497 | (2) |
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499 | (2) |
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Array Processor Implementation |
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501 | (2) |
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Array Processor Performance |
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503 | (5) |
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504 | (3) |
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References and Further Readings |
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507 | (1) |
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Shared-Memory Multiprocessing |
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508 | (20) |
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Centralized Shared Memory |
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508 | (4) |
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Multiple Caches and Cache Coherence |
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512 | (2) |
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Implementing Symmetric Multiprocessors |
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514 | (3) |
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Distributed Shared Memory |
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517 | (2) |
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Directories to Guide Data Access |
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519 | (2) |
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Implementing Asymmetric Multiprocessors |
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521 | (7) |
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524 | (3) |
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References and Further Readings |
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527 | (1) |
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Distributed Multicomputing |
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528 | (20) |
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Communication by Message Passing |
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528 | (4) |
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532 | (3) |
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Message Composition and Routing |
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535 | (2) |
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Building and Using Multicomputers |
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537 | (3) |
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Network-Based Distributed Computing |
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540 | (2) |
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Grid Computing and Beyond |
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542 | (6) |
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543 | (4) |
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References and Further Readings |
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547 | (1) |
Index |
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548 | |