Computer Architecture From Microprocessors to Supercomputers

by
Format: Hardcover
Pub. Date: 2005-02-17
Publisher(s): Oxford University Press
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Summary

Computer Architecture: From Microprocessors to Supercomputers provides a comprehensive introduction to this thriving and exciting field. Emphasizing both underlying theory and actual designs, the book covers a wide array of topics and links computer architecture to other subfields ofcomputing. The material is presented in lecture-sized chapters that make it easy for students to understand the relationships between various topics and to see the "big picture." The short chapters also allow instructors to order topics in the course as they like. The text is divided into seven parts, each containing four chapters. Part I provides context and reviews prerequisite topics including digital computer technology and computer system performance. Part II discusses instruction-set architecture. The next two parts cover the central processing unit.Part III describes the structure of arithmetic/logic units and Part IV is devoted to data path and control circuits. Part V deals with the memory system. Part VI covers input/output and interfacing topics and Part VII introduces advanced architectures. Computer Architecture: From Microprocessors to Supercomputers is designed for introductory courses and is suitable for students majoring in electrical engineering, computer science, or computer engineering. BL An Instructor's Manual (0-19-522213-X) and CD with PowerPointRG presentations (0-19-522219-9) are available to adopters. BL Visit the companion website at: http://www.ece.ucsb.edu/Faculty/Parhami/text_comp_arch.htm

Author Biography


Behrooz Parhami is Professor of Computer Engineering at the University of California, Santa Barbara. He has written several textbooks, including Computer Arithmetic (OUP, 2000), and more than 200 research papers. He is a fellow of both the Institute of Electrical and Electronics Engineers (IEEE) and the British Computer Society (BCS). He is a member of the Association for Computing Machinery (ACM), and a distinguished member of the Informatics Society of Iran, for which he served as a founding member and the first president.

Table of Contents

Structure at a Glance vi
Preface xv
PART 1 BACKGROUND AND MOTIVATION
1(80)
Combinational Digital Circuits
3(18)
Signals, Logic Operators, and Gates
3(4)
Boolean Functions and Expressions
7(1)
Designing Gate Networks
8(3)
Useful Combinational Parts
11(2)
Programmable Combinational Parts
13(2)
Timing and Circuit Considerations
15(6)
Problems
17(2)
References and Further Readings
19(2)
Digital Circuits with Memory
21(17)
Latches, Flip-Flops, and Registers
21(3)
Finite-State Machines
24(1)
Designing Sequential Circuits
25(3)
Useful Sequential Parts
28(2)
Programmable Sequential Parts
30(2)
Clocks and Timing of Events
32(6)
Problems
34(3)
References and Further Readings
37(1)
Computer System Technology
38(21)
From Components to Applications
39(2)
Computer Systems and Their Parts
41(4)
Generations of Progress
45(3)
Processor and Memory Technologies
48(3)
Peripherals, I/O, and Communications
51(3)
Software Systems and Applications
54(5)
Problems
56(2)
References and Further Readings
58(1)
Computer Performance
59(22)
Cost, Performance, and Cost/Performance
59(3)
Defining Computer Performance
62(3)
Performance Enhancement and Amdahl's Law
65(2)
Performance Measurement vs Modeling
67(5)
Reporting Computer Performance
72(2)
The Quest for Higher Performance
74(7)
Problems
76(3)
References and Further Readings
79(2)
PART 2 INSTRUCTION-SET ARCHITECTURE
81(76)
Instructions and Addressing
83(20)
Abstract View of Hardware
83(3)
Instruction Formats
86(3)
Simple Arithmetic and Logic Instructions
89(2)
Load and Store Instructions
91(2)
Jump and Branch Instructions
93(4)
Addressing Modes
97(6)
Problems
99(3)
References and Further Readings
102(1)
Procedures and Data
103(20)
Simple Procedure Calls
103(3)
Using the Stack for Data Storage
106(2)
Parameters and Results
108(2)
Data Types
110(3)
Arrays and Pointers
113(3)
Additional Instructions
116(7)
Problems
120(2)
References and Further Readings
122(1)
Assembly Language Programs
123(16)
Machine and Assembly Languages
123(3)
Assembler Directives
126(1)
Pseudoinstructions
127(3)
Macroinstructions
130(1)
Linking and Loading
131(2)
Running Assembler Programs
133(6)
Problems
136(2)
References and Further Readings
138(1)
Instruction-Set Variations
139(18)
Complex Instructions
139(2)
Alternative Addressing Modes
141(4)
Variations in Instruction Formats
145(2)
Instruction-Set Design and Evolution
147(1)
The RISC/CISC Dichotomy
148(3)
Where to Draw the Line
151(6)
Problems
154(2)
References and Further Readings
156(1)
PART 3 THE ARITHMETIC/LOGIC UNIT
157(84)
Number Representation
159(19)
Positional Number Systems
159(3)
Digit Sets and Encodings
162(3)
Number-Radix Conversion
165(1)
Signed Integers
166(3)
Fixed-Point Numbers
169(2)
Floating-Point Numbers
171(7)
Problems
174(2)
References and Further Readings
176(2)
Adders and Simple ALUs
178(19)
Simple Adders
178(2)
Carry Propagation Networks
180(3)
Counting and Incrementation
183(2)
Design of Fast Adders
185(3)
Logic and Shift Operations
188(3)
Multifunction ALUs
191(6)
Problems
193(3)
References and Further Readings
196(1)
Multipliers and Dividers
197(22)
Shift-Add Multiplication
197(4)
Hardware Multipliers
201(3)
Programmed Multiplication
204(2)
Shift-Subtract Division
206(4)
Hardware Dividers
210(3)
Programmed Division
213(6)
Problems
215(3)
References and Further Readings
218(1)
Floating-Point Arithmetic
219(22)
Rounding Modes
219(5)
Special Values and Exceptions
224(2)
Floating-Point Addition
226(3)
Other Floating-Point Operations
229(1)
Floating-Point Instructions
230(3)
Result Precision and Errors
233(8)
Problems
237(2)
References and Further Readings
239(2)
PART 4 DATA PATH AND CONTROL
241(74)
Instruction Execution Steps
243(15)
A Small Set of Instructions
244(2)
The Instruction Execution Unit
246(1)
A Single-Cycle Data Path
247(2)
Branching and Jumping
249(1)
Deriving the Control Signals
250(3)
Performance of the Single-Cycle Design
253(5)
Problems
255(2)
References and Further Readings
257(1)
Control Unit Synthesis
258(19)
A Multicycle Implementation
258(3)
Clock Cycle and Control Signals
261(3)
The Control State Machine
264(2)
Performance of the Multicycle Design
266(1)
Microprogramming
267(4)
Dealing with Exceptions
271(6)
Problems
273(3)
References and Further Readings
276(1)
Pipelined Data Paths
277(20)
Pipelining Concepts
277(4)
Pipeline Stalls or Bubbles
281(3)
Pipeline Timing and Performance
284(2)
Pipelined Data Path Design
286(3)
Pipelined Control
289(2)
Optimal Pipelining
291(6)
Problems
293(3)
References and Further Readings
296(1)
Pipeline Performance Limits
297(18)
Data Dependencies and Hazards
297(3)
Data Forwarding
300(2)
Pipeline Branch Hazards
302(2)
Branch Prediction
304(2)
Advanced Pipelining
306(3)
Exceptions in a Pipeline
309(6)
Problems
310(3)
References and Further Readings
313(2)
PART 5 MEMORY SYSTEM DESIGN
315(76)
Main Memory Concepts
317(18)
Memory Structure and SRAM
317(3)
DRAM and Refresh Cycles
320(3)
Hitting the Memory Wall
323(2)
Pipelined and Interleaved Memory
325(2)
Nonvolatile Memory
327(2)
The Need for a Memory Hierarchy
329(6)
Problems
331(3)
References and Further Readings
334(1)
Cache Memory Organization
335(18)
The Need for a Cache
335(3)
What Makes a Cache Work?
338(3)
Direct-Mapped Cache
341(1)
Set-Associative Cache
342(3)
Cache and Main Memory
345(1)
Improving Cache Performance
346(7)
Problems
348(4)
References and Further Readings
352(1)
Mass Memory Concepts
353(18)
Disk Memory Basics
353(3)
Organizing Data on Disk
356(3)
Disk Performance
359(1)
Disk Caching
360(1)
Disk Arrays and RAID
361(4)
Other Types of Mass Memory
365(6)
Problems
367(3)
References and Further Readings
370(1)
Virtual Memory and Paging
371(20)
The Need for Virtual Memory
371(2)
Address Translation in Virtual Memory
373(3)
Translation Lookaside Buffer
376(3)
Page Replacement Policies
379(3)
Main and Mass Memories
382(1)
Improving Virtual Memory Performance
383(8)
Problems
386(3)
References and Further Readings
389(2)
PART 6 INPUT/OUTPUT AND INTERFACING
391(74)
Input/Output Devices
393(18)
Input/Output Devices and Controllers
393(2)
Keyboard and Mouse
395(2)
Visual Display Units
397(3)
Hard-Copy Input/Output Devices
400(4)
Other Input/Output Devices
404(2)
Networking of Input/Output Devices
406(5)
Problems
408(2)
References and Further Readings
410(1)
Input/Output Programming
411(18)
I/O Performance and Benchmarks
411(2)
Input/Output Addressing
413(3)
Scheduled I/O: Polling
416(1)
Demand-Based I/O: Interrupts
417(1)
I/O Data Transfer and DMA
418(3)
Improving I/O Performance
421(8)
Problems
425(3)
References and Further Readings
428(1)
Buses, Links, and Interfacing
429(20)
Intra-and Intersystem Links
429(4)
Buses and Their Appeal
433(2)
Bus Communication Protocols
435(3)
Bus Arbitration and Performance
438(2)
Basics of Interfacing
440(1)
Interfacing Standards
441(8)
Problems
445(2)
References and Further Readings
447(2)
Context Switching and Interrupts
449(16)
System Calls for I/O
449(2)
Interrupts, Exceptions, and Traps
451(2)
Simple Interrupt Handling
453(3)
Nested Interrupts
456(2)
Types of Context Switching
458(2)
Threads and Multithreading
460(5)
Problems
462(2)
References and Further Readings
464(1)
PART 7 ADVANCED ARCHITECTURES
465(83)
Road to Higher Performance
467(23)
Past and Current Performance Trends
467(3)
Performance-Driven ISA Extensions
470(3)
Instruction-Level Parallelism
473(3)
Speculation and Value Prediction
476(3)
Special-Purpose Hardware Accelerators
479(3)
Vector, Array, and Parallel Processing
482(8)
Problems
485(3)
References and Further Readings
488(2)
Vector and Array Processing
490(18)
Operations on Vectors
491(2)
Vector Processor Implementation
493(4)
Vector Processor Performance
497(2)
Shared-Control Systems
499(2)
Array Processor Implementation
501(2)
Array Processor Performance
503(5)
Problems
504(3)
References and Further Readings
507(1)
Shared-Memory Multiprocessing
508(20)
Centralized Shared Memory
508(4)
Multiple Caches and Cache Coherence
512(2)
Implementing Symmetric Multiprocessors
514(3)
Distributed Shared Memory
517(2)
Directories to Guide Data Access
519(2)
Implementing Asymmetric Multiprocessors
521(7)
Problems
524(3)
References and Further Readings
527(1)
Distributed Multicomputing
528(20)
Communication by Message Passing
528(4)
Interconnection Networks
532(3)
Message Composition and Routing
535(2)
Building and Using Multicomputers
537(3)
Network-Based Distributed Computing
540(2)
Grid Computing and Beyond
542(6)
Problems
543(4)
References and Further Readings
547(1)
Index 548

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