Design of Energy-Efficient Application-Specific Instruction Set Processors

by ;
Format: Hardcover
Pub. Date: 2004-06-01
Publisher(s): Kluwer Academic Pub
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Summary

After a brief introduction to low-power VLSI design, the design space of ASIP instruction set architectures (ISAs) is introduced with a special focus on important features for digital signal processing. Based on the degrees of freedom offered by this design space, a consistent ASIP design flow is proposed: this design flow starts with a given application and uses incremental optimization of the ASIP hardware, of ASIP coprocessors and of the ASIP software by using a top-down approach and by applying application-specific modifications on all levels of design hierarchy. A broad range of real-world signal processing applications serves as vehicle to illustrate each design decision and provides a hands-on approach to ASIP design. Finally, two complete case studies demonstrate the feasibility and the efficiency of the proposed methodology and quantitatively evaluate the benefits of ASIPs in an industrial context.

Table of Contents

Foreword
Acknowledgements
About the Authors
Introduction
Focus and Related Work
Focus of this Work
Previous Work
Differences to Previous Work
Efficient Low-Power Hardware Design
Metrics of the Implementation and the Hardware Design Methodology
Basics of Low-Energy Hardware Design
Techniques to Reduce the Energy Consumption
Concluding Remarks
Application-Specific Processor Architectures
Definitions of ASIP Related Terms
ASIP Applications
ASIP Design Space
Critical Factors for Energy-Efficient ASIPs
Concluding Remarks
The ASIP Design Flow
Example Applications
Application Profiling and Partitioning
Combined ASIP HW/SW Synthesis and Profiling
Verification
Concluding Remarks
The ASIP Design Environment
The LISA Language
The LISA Design Environment
Extensions to the LISA Design Environment
Concluding Remarks
Case Studies
Case Study I: BVD-T Acquisition and Tracking
Case Study II: Linear Algebra Kernels and Eigenvalue Decomposition
Concluding Remarks
Summary
ASIP Development Using LIS 2.0
The LISA 2.0 Language
Design Space Exploration
Design Implementation
Software Tools Generation
System Integration
Summary
Computational Kernels
The CORDIC Algorithm
FIR Filter
The Fast Fourier Transform
Vector/Matrix Operations
Complex EVD Using a Jacobi-like Algorithm
ICORE Instruction Set Architecture
Processor Resources
Pipeline Organization
Instruction Summary
Exceptions to the Hidden Pipeline Model
ICORE Memory Organization and I/O Space
Instruction Coding
Different ICORE Pipeline Organizations
ICORE HDL Description Templates
Generic Register File Entity
Generic Bit-Manipulation Unit
Area, Power and Design Time for ICORE
Acronyms
Bibliography
Table of Contents provided by Publisher. All Rights Reserved.

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