Preface |
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xi | |
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1 | (40) |
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3 | (1) |
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Binary to Decimal Conversion |
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4 | (2) |
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Decimal to Binary Conversion |
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6 | (3) |
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9 | (1) |
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Binary to Octal Conversion |
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10 | (1) |
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Octal to Binary Conversion |
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11 | (1) |
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Hexadecimal Number System |
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12 | (2) |
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Binary to Hexadecimal Conversion |
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14 | (1) |
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Hexadecimal to Binary Conversion |
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15 | (1) |
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Binary-Coded Decimal (BCD) |
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16 | (6) |
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22 | (1) |
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23 | (3) |
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Troubleshooting a 4-Bit Adder |
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26 | (15) |
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28 | (1) |
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29 | (1) |
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30 | (2) |
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Lab 1A 7483 4-Bit Full Adder |
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32 | (5) |
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Lab 1B 4008 4-Bit Full Adder |
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37 | (4) |
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41 | (48) |
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43 | (1) |
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43 | (2) |
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45 | (4) |
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49 | (5) |
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54 | (4) |
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58 | (3) |
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Data Control Enable/Inhibit |
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61 | (1) |
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61 | (1) |
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62 | (1) |
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63 | (1) |
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64 | (1) |
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65 | (1) |
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66 | (1) |
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66 | (1) |
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66 | (1) |
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67 | (1) |
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67 | (1) |
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67 | (1) |
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Programming a PLD (Optional) |
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68 | (4) |
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72 | (17) |
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74 | (1) |
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75 | (1) |
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76 | (6) |
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82 | (3) |
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85 | (4) |
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Waveforms and Boolean Algebra |
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89 | (64) |
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91 | (2) |
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Delayed-Clock and Shift-Counter Waveforms |
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93 | (6) |
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99 | (1) |
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100 | (7) |
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107 | (5) |
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112 | (11) |
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123 | (2) |
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Reducing Boolean Expressions Using Karnaugh Maps |
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125 | (2) |
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Programmable Logic Devices |
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127 | (4) |
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Programming a PLD (Optional) |
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131 | (3) |
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Troubleshooting Combinational Logic Circuits |
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134 | (19) |
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135 | (2) |
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137 | (1) |
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138 | (9) |
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147 | (3) |
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150 | (3) |
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153 | (42) |
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155 | (3) |
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158 | (1) |
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159 | (1) |
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160 | (2) |
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162 | (1) |
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163 | (3) |
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Even/Odd-Parity Generator |
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166 | (2) |
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168 | (2) |
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9-Bit Parity Generator/Checker |
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170 | (4) |
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174 | (5) |
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Programming a CPLD (Optional) |
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179 | (3) |
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Troubleshooting Exclusive-OR Circuits |
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182 | (13) |
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184 | (1) |
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184 | (1) |
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185 | (5) |
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190 | (1) |
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Lab 4B Parity Generator/Checker |
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191 | (4) |
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195 | (56) |
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197 | (1) |
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198 | (7) |
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Binary 1's Complement Subtraction |
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205 | (2) |
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1's Complement Adder/Subtractor Circuit |
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207 | (4) |
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Binary 2's Complement Subtraction |
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211 | (3) |
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2's Complement Adder/Subtractor Circuit |
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214 | (5) |
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Signed 2's Complement Numbers |
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219 | (6) |
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Binary-Coded-Decimal Addition |
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225 | (2) |
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Binary-Coded-Decimal Adder Circuit |
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227 | (2) |
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Arithmetic Logic Unit (ALU) |
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229 | (2) |
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Programming a CPLD (Optional) |
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231 | (6) |
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Troubleshooting Adder Circuits |
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237 | (14) |
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239 | (1) |
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239 | (2) |
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241 | (5) |
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246 | (2) |
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248 | (3) |
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Specifications and Open-Collector Gates |
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251 | (42) |
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253 | (1) |
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TTL Electrical Characteristics |
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253 | (6) |
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259 | (1) |
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TTL Switching Characteristics |
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259 | (4) |
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263 | (2) |
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Open-Collector Applications |
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265 | (2) |
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267 | (1) |
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267 | (3) |
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270 | (3) |
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273 | (2) |
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275 | (1) |
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Emitter-Coupled Logic (ECL) |
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276 | (2) |
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Interfacing ECL to Other Logic Families |
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278 | (2) |
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280 | (2) |
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CPLD Specifications (Optional) |
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282 | (1) |
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Troubleshooting TTL and CMOS Devices |
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283 | (10) |
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284 | (1) |
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285 | (1) |
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286 | (3) |
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Lab 6A Specifications and Open-Collector Gates |
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289 | (2) |
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Lab 6B Specifications and Open-Drain Inverters |
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291 | (2) |
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293 | (32) |
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Introduction to Flip-Flops |
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295 | (1) |
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Crossed Nand Set-Reset Flip-Flops |
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295 | (2) |
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Crossed NOR SET-RESET Flip-Flops |
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297 | (2) |
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Comparison of the Crossed NAND and the Crossed NOR SET-RESET Flip-Flops |
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299 | (1) |
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Using a SET-RESET Flip-Flop as a Debounce Switch |
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300 | (1) |
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The Gated SET-RESET Flip-Flop |
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301 | (2) |
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The Transparent D Flip-Flop |
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303 | (2) |
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The Master-Slave D Flip-Flop |
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305 | (5) |
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The Pulse Edge-Triggered D Flip-Flop |
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310 | (1) |
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Programming a CPLD (Optional) |
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311 | (4) |
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Troubleshooting a Digital Circuit |
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315 | (10) |
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318 | (1) |
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318 | (1) |
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319 | (3) |
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322 | (1) |
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323 | (2) |
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Master-Slave D and JK Flip-Flops |
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325 | (28) |
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Toggling a Master-Slave D Flip-Flop |
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327 | (1) |
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328 | (3) |
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331 | (1) |
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332 | (3) |
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335 | (1) |
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Programming a CPLD (Optional) |
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336 | (4) |
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Troubleshooting JK Flip-Flops |
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340 | (13) |
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342 | (1) |
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343 | (1) |
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344 | (5) |
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Lab 8A Shift Counter and Delayed Clock |
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349 | (2) |
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351 | (2) |
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353 | (38) |
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Shift Register Constructed From JK Flip-Flops |
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355 | (1) |
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356 | (1) |
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357 | (2) |
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Serial Data Transmission Formats |
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359 | (3) |
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362 | (3) |
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365 | (3) |
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368 | (2) |
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Programming a CPLD (Optional) |
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370 | (4) |
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Troubleshooting an RS-232C System |
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374 | (2) |
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376 | (15) |
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378 | (1) |
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378 | (1) |
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379 | (3) |
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382 | (6) |
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388 | (3) |
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391 | (32) |
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393 | (1) |
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The Decode-and-Clear Method of Making a Divide-by-N Ripple counter |
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394 | (2) |
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The Divide-by-N Synchronous Counter |
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396 | (3) |
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399 | (2) |
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401 | (2) |
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403 | (3) |
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The Divide-by-N1/2 Counter |
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406 | (3) |
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Programming a CPLD (Optional) |
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409 | (5) |
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414 | (9) |
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416 | (1) |
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416 | (1) |
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417 | (3) |
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420 | (2) |
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422 | (1) |
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Schmitt-Trigger Inputs and Clocks |
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423 | (22) |
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The Schmitt-Trigger Input |
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425 | (1) |
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Using a Schmitt Trigger to Square Up an Irregular Wave |
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425 | (1) |
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426 | (2) |
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The 555 Timer Used as a Clock |
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428 | (6) |
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434 | (1) |
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Troubleshooting Clock Circuits |
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435 | (10) |
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437 | (1) |
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437 | (1) |
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438 | (3) |
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Lab 11A Schmitt Triggers and Clocks |
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441 | (2) |
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443 | (2) |
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445 | (18) |
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A One-Shot Debounce Switch |
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447 | (1) |
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447 | (2) |
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The Retriggerable One-Shot |
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449 | (1) |
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The Nonretriggerable One-Shot |
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450 | (1) |
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451 | (2) |
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453 | (1) |
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453 | (3) |
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Troubleshooting One-Shots |
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456 | (7) |
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458 | (1) |
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458 | (1) |
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459 | (2) |
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461 | (1) |
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462 | (1) |
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Digital-to-Analog and Analog-to-Digital Conversions |
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463 | (28) |
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Resistor Networks for Digital-to-Analog Conversion |
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465 | (4) |
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The TTL Digital-to-Analog Converter |
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469 | (2) |
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Analog-to-Digital Conversion Using Voltage Comparators |
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471 | (2) |
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The Count-Up and Compare Analog-to-Digital Converter |
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473 | (2) |
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The Successive Approximation Analog-to-Digital Converter |
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475 | (3) |
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The DAC0830 Digital-to-Analog Converter Integrated Circuit |
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478 | (3) |
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Making the Logic for a 3-Bit Voltage Comparator Analog-to-Digital Converter |
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481 | (1) |
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Troubleshooting Digital-to-Analog Converters |
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482 | (9) |
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483 | (2) |
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485 | (1) |
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485 | (2) |
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Lab 13A Digital-to-Analog and Analog-to-Digital |
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487 | (2) |
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Lab 13B Analog-to-Digital Converters |
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489 | (2) |
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Decoders, Multiplexers, Demultiplexers and Displays |
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491 | (40) |
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493 | (2) |
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495 | (1) |
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495 | (1) |
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Using a Multiplexer to Reproduce a Desired Truth Table |
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496 | (3) |
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Multiplexer and Demultiplexer ICS |
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499 | (2) |
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The 8-Trace Oscilloscope Multiplexer |
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501 | (1) |
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502 | (2) |
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The Seven-Segment Display |
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504 | (3) |
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The Liquid Crystal Display |
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507 | (4) |
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Programming a CPLD (Optional) |
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511 | (8) |
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519 | (12) |
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522 | (1) |
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523 | (1) |
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523 | (3) |
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Lab 14A Multiplexers, Leds, and Seven-Segment Displays |
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526 | (3) |
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529 | (2) |
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Tri-State Gates and Interfacing to High Current |
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531 | (22) |
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533 | (2) |
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Tri-State Inverters and Buffers |
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535 | (2) |
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Computer Buses and the Tri-State Gate |
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537 | (2) |
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Buffering to High Current and High Voltage |
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539 | (3) |
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Multiplexing Seven-Segment LED Displays |
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542 | (2) |
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Isolating One Circuit from Another with Optocouplers |
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544 | (1) |
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Insulated Gate Bipolar Transistor (IGBT) |
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545 | (1) |
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Troubleshooting High-Current Digital Circuits |
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546 | (7) |
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548 | (1) |
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548 | (1) |
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549 | (2) |
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551 | (1) |
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552 | (1) |
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Memories and an Introduction to Microcomputers |
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553 | (34) |
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The Microcomputer and Its Parts |
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555 | (1) |
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The Central Processing Unit |
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555 | (3) |
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558 | (1) |
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558 | (1) |
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559 | (2) |
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561 | (1) |
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562 | (2) |
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564 | (1) |
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565 | (2) |
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The Input/Output of The Computer |
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567 | (3) |
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570 | (2) |
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572 | (2) |
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574 | (2) |
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576 | (11) |
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582 | (1) |
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582 | (2) |
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584 | (3) |
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587 | (22) |
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589 | (4) |
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593 | (2) |
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595 | (8) |
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Nand Gates, MOS, and CMOS |
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603 | (6) |
Glossary |
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609 | (10) |
Answers to Self-Check and Odd-Numbered Questions and Problems |
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619 | (84) |
Index |
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703 | |