Digital Systems Testing and Testable Design,9780780310629

Digital Systems Testing and Testable Design

by ; ;
Edition: 1st
ISBN13: 9780780310629
ISBN10: 0780310624
Format: Hardcover
Pub. Date: 1994-09-27
Publisher(s): Wiley-IEEE Press
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Summary

This updated printing of the leading text and reference in digital systems testing and testable design provides comprehensive, state-of-the-art coverage of the field. Included are extensive discussions of test generation, fault modeling for classic and new technologies, simulation, fault simulation, design for testability, built-in self-test, and diagnosis. Complete with numerous problems, this book is a must-have for test engineers, ASIC and system designers, and CAD developers, and advanced engineering students will find this book an invaluable tool to keep current with recent changes in the field.

Author Biography

Miron Abramovici is a Distinguished Member of the Technical Staff at AT&T Bell Laboratories in Murray Hill, and an Adjunct Professor of Computer Engineering at the Illinois Institute of Technology in Chicago.

Table of Contents

Preface xiii
How This Book Was Written xvii
Introduction
1(8)
Modeling
9(30)
Basic Concepts
9(1)
Functional Modeling at the Logic Level
10(10)
Truth Tables and Primitive Cubes
10(3)
State Tables and Flow Tables
13(4)
Binary Decision Diagrams
17(1)
Programs as Functional Models
18(2)
Functional Modeling at the Register Level
20(4)
Basic RTL Constructs
20(3)
Timing Modeling in RTLs
23(1)
Internal RTL Models
24(1)
Structural Models
24(8)
External Representation
24(2)
Structural Properties
26(3)
Internal Representation
29(2)
Wired Logic and Bidirectionality
31(1)
Level of Modeling
32(7)
References
35(1)
Problems
36(3)
Logic Simulation
39(54)
Applications
39(2)
Problems in Simulation-Based Design Verification
41(1)
Types of Simulation
42(1)
The Unknown Logic Value
43(3)
Compiled Simulation
46(3)
Event-Driven Simulation
49(3)
Delay Models
52(4)
Delay Modeling for Gates
52(2)
Delay Modeling for Functional Elements
54(1)
Delay Modeling in RTLs
55(1)
Other Aspects of Delay Modeling
55(1)
Element Evaluation
56(4)
Hazard Detection
60(4)
Gate-Level Event-Driven Simulation
64(15)
Transition-Independent Nominal Transport Delays
64(7)
Other Logic Values
71(1)
Tristate Logic
71(1)
MOS Logic
72(2)
Other Delay Models
74(1)
Rise and Fall Delays
74(2)
Inertial Delays
76(1)
Ambiguous Delays
76(1)
Oscillation Control
77(2)
Simulation Engines
79(14)
References
84(2)
Problems
86(7)
Fault Modeling
93(38)
Logical Fault Models
93(2)
Fault Detection and Redundancy
95(11)
Combinational Circuits
95(8)
Sequential Circuits
103(3)
Fault Equivalence and Fault Location
106(3)
Combinational Circuits
106(2)
Sequential Circuits
108(1)
Fault Dominance
109(9)
Combinational Circuits
109(1)
Sequential Circuits
110(8)
The Single Stuck-Fault Model
118(4)
Stuck RTL Variables
122(1)
Fault Variables
122(9)
References
123(3)
Problems
126(5)
Fault Simulation
131(50)
Applications
131(3)
General Fault Simulation Techniques
134(21)
Serial Fault Simulation
134(1)
Common Concepts and Terminology
134(1)
Parallel Fault Simulation
135(4)
Deductive Fault Simulation
139(1)
Two-Valued Deductive Simulation
140(5)
Three-Valued Deductive Simulation
145(1)
Concurrent Fault Simulation
146(8)
Comparison
154(1)
Fault Simulation for Combinational Circuits
155(12)
Parallel-Pattern Single-Fault Propagation
156(1)
Critical Path Tracing
157(10)
Fault Sampling
167(2)
Statistical Fault Analysis
169(3)
Concluding Remarks
172(9)
References
173(4)
Problems
177(4)
Testing For Single Stuck Faults
181(108)
Basic Issues
181(1)
ATG for SSFs in Combinational Circuits
182(67)
Fault-Oriented ATG
182(7)
Common Concepts
189(7)
Algorithms
196(17)
Selection Criteria
213(7)
Fault-Independent ATG
220(6)
Random Test Generation
226(1)
The Quality of a Random Test
227(1)
The Length of a Random Test
227(2)
Determining Detection Probabilities
229(5)
RTG with Nonuniform Distributions
234(1)
Combined Deterministic/Random TG
235(5)
ATG Systems
240(6)
Other TG Methods
246(3)
ATG for SSFs in Sequential Circuits
249(23)
TG Using Iterative Array Models
249(13)
Simulation-Based TG
262(2)
TG Using RTL Models
264(1)
Extensions of the D-Algorithm
265(4)
Heuristic State-Space Search
269(2)
Random Test Generation
271(1)
Concluding Remarks
272(17)
References
274(7)
Problems
281(8)
Testing for Bridging Faults
289(16)
The Bridging-Fault Model
289(3)
Detection of Nonfeedback Bridging Faults
292(2)
Detection of Feedback Bridging Faults
294(3)
Bridging Faults Simulation
297(4)
Test Generation for Bridging Faults
301(1)
Concluding Remarks
302(3)
References
302(1)
Problems
302(3)
Functional Testing
305(38)
Basic Issues
305(1)
Functional Testing Without Fault Models
305(8)
Heuristic Methods
305(4)
Functional Testing with Binary Decision Diagrams
309(4)
Exhaustive and Pseudoexhaustive Testing
313(10)
Combinational Circuits
313(1)
Partial-Dependence Circuits
313(1)
Partitioning Techniques
314(1)
Sequential Circuits
315(2)
Iterative Logic Arrays
317(6)
Functional Testing with Specific Fault Models
323(14)
Functional Fault Models
323(2)
Fault Models for Microprocessors
325(2)
Fault Model for the Register-Decoding Function
327(1)
Fault Model for the Instruction-Decoding and Instruction-Sequencing Function
328(1)
Fault Model for the Data-Storage Function
329(1)
Fault Model for the Data-Manipulation Function
329(1)
Test Generation Procedures
330(1)
Testing the Register-Decoding Function
330(2)
Testing the Instruction-Decoding and Instruction-Sequencing Function
332(4)
Testing the Data-Storage and Data-Transfer Functions
336(1)
A Case Study
337(1)
Concluding Remarks
337(6)
References
338(3)
Problems
341(2)
Design for Testability
343(78)
Testability
343(4)
Trade-Offs
344(1)
Controllability and Observability
345(2)
Ad Hoc Design for Testability Techniques
347(11)
Test Points
347(4)
Initialization
351(1)
Monostable Multivibrators
351(2)
Oscillators and Clocks
353(1)
Partitioning Counters and Shift Registers
354(1)
Partitioning of Large Combinational Circuits
355(1)
Logical Redundancy
356(2)
Global Feedback Paths
358(1)
Controllability and Observability by Means of Scan Registers
358(6)
Generic Boundary Scan
363(1)
Generic Scan-Based Designs
364(4)
Full Serial Integrated Scan
365(1)
Isolated Serial Scan
366(2)
Nonserial Scan
368(1)
Storage Cells for Scan Designs
368(6)
Classical Scan Designs
374(8)
Scan Design Costs
382(1)
Board-Level and System-Level DFT Approaches
382(3)
System-Level Busses
383(1)
System-Level Scan Paths
383(2)
Some Advanced Scan Concepts
385(10)
Multiple Test Session
385(1)
Partial Scan Using I-Paths
386(4)
BALLAST--A Structured Partial Scan Design
390(5)
Boundary Scan Standards
395(26)
Background
395(3)
Boundary Scan Cell
398(1)
Board and Chip Test Modes
399(2)
The Test Bus
401(1)
Test Bus Circuitry
402(1)
The TAP Controller
402(5)
Registers
407(1)
References
408(4)
Problems
412(9)
Compression Techniques
421(36)
General Aspects of Compression Techniques
421(2)
Ones-Count Compression
423(2)
Transition-Count Compression
425(3)
Parity-Check Compression
428(1)
Syndrome Testing
429(3)
Signature Analysis
432(15)
Theory and Operation of Linear Feedback Shift Registers
432(9)
LFSRs Used as Signature Analyzers
441(4)
Multiple-Input Signature Registers
445(2)
Concluding Remarks
447(10)
References
448(4)
Problems
452(5)
Built-In Self-Test
457(84)
Introduction to BIST Concepts
457(3)
Hardcore
458(1)
Levels of Test
459(1)
Test-Pattern Generation for BIST
460(17)
Exhaustive Testing
460(1)
Pseudorandom Testing
460(1)
Pseudoexhaustive Testing
461(1)
Logical Segmentation
462(1)
Constant-Weight Patterns
463(3)
Identification of Test Signal Inputs
466(5)
Test Pattern Generators for Pseudoexhaustive Tests
471(5)
Physical Segmentation
476(1)
Generic Off-Line BIST Architectures
477(6)
Specific BIST Architectures
483(31)
A Centralized and Separate Board-Level BIST Architecture (CSBL)
483(1)
Built-In Evaluation and Self-Test (BEST)
483(1)
Random-Test Socket (RTS)
484(2)
LSSD On-Chip Self-Test (LOCST)
486(2)
Self-Testing Using MISR and Parallel SRSG (STUMPS)
488(2)
A Concurrent BIST Architecture (CBIST)
490(1)
A Centralized and Embedded BIST Architecture with Boundary Scan (CEBS)
490(2)
Random Test Data (RTD)
492(1)
Simultaneous Self-Test (SST)
493(2)
Cyclic Analysis Testing System (CATS)
495(1)
Circular Self-Test Path (CSTP)
496(5)
Built-In Logic-Block Observation (BILBO)
501(9)
Case Study
510(3)
Summary
513(1)
Some Advanced BIST Concepts
514(9)
Test Schedules
515(2)
Control of BILBO Registers
517(3)
Partial-Intrusion BIST
520(3)
Design for Self-Test at Board Level
523(18)
References
524(8)
Problems
532(9)
Logic-Level Diagnosis
541(28)
Basic Concepts
541(2)
Fault Dictionary
543(6)
Guided-Probe Testing
549(5)
Diagnosis by UUT Reduction
554(2)
Fault Diagnosis for Combinational Circuits
556(1)
Expert Systems for Diagnosis
557(2)
Effect-Cause Analysis
559(5)
Diagnostic Reasoning Based on Structure and Behavior
564(5)
References
566(2)
Problems
568(1)
Self-Checking Design
569(24)
Basic Concepts
569(1)
Application of Error-Detecting and Error-Correcting Codes
570(7)
Multiple-Bit Errors
577(1)
Checking Circuits and Self-Checking
578(1)
Self-Checking Checkers
579(1)
Parity-Check Function
580(1)
Totally Self-Checking m/n Code Checkers
581(3)
Totally Self-Checking Equality Checkers
584(1)
Self-Checking Berger Code Checkers
584(1)
Toward a General Theory of Self-Checking Combinational Circuits
585(2)
Self-Checking Sequential Circuits
587(6)
References
589(1)
Problems
590(3)
PLA Testing
593(40)
Introduction
593(1)
PLA Testing Problems
594(3)
Fault Models
594(3)
Problems with Traditional Test Generation Methods
597(1)
Test Generation Algorithms for PLAs
597(3)
Deterministic Test Generation
598(1)
Semirandom Test Generation
599(1)
Testable PLA Designs
600(18)
Concurrent Testable PLAs with Special Coding
600(1)
PLA with Concurrent Error Detection by a Series of Checkers
600(1)
Concurrent Testable PLAs Using Modified Berger Code
601(2)
Parity Testable PLAs
603(1)
PLA with Universal Test Set
603(2)
Autonomously Testable PLAs
605(1)
A Built-In Self-Testable PLA Design with Cumulative Parity Comparison
606(2)
Signature-Testable PLAs
608(1)
PLA with Multiple Signature Analyzers
609(1)
Self-Testable PLAs with Single Signature Analyzer
609(1)
Partioning and Testing of PLAs
610(1)
PLA with BILBOs
611(3)
Parallel-Testable PLAs
614(1)
Divide-and-Conquer Strategy for Testable PLA Design
614(1)
Fully-Testable PLA Designs
615(3)
Evaluation of PLA Test Methodologies
618(15)
Measures of TDMs
618(1)
Resulting Effect on the Original Design
619(1)
Requirements on Test Environment
619(1)
Evaluation of PLA Test Techniques
620(7)
References
627(3)
Problems
630(3)
System-Level Diagnosis
633(14)
A Simple Model of System-Level Diagnosis
633(5)
Generalizations of the PMC Model
638(9)
Generalizations of the System Diagnostic Graph
638(2)
Generalization of Possible Test Outcomes
640(1)
Generalization of Diagnosability Measures
641(3)
References
644(1)
Problems
645(2)
Index 647

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