Summary
1156F-7 Genetic algorithms mimic the natural process of evolution, helping engineers optimize their designs by using the principle of "survival of the fittest." VLSI is especially suited to benefit from genetic algorithms - and this comprehensive book shows you how to get the best results, fast. You'll discover how genetic algorithms work and how you can use them in a wide variety of VLSI design, layout, and test automation tasks, including: Circuit partitioning Macro cell routing, including Steiner problems and global routing Standard cell and macro cell placement Circuit segmentation, FPGA mapping and pseudo-exhaustive testing Automatic test generation including compaction, eterministic/genetic test hybrids and integration of finite state machine sequences Peak power estimation You'll find essential insights into problem encoding and fitness functions; coverage of advanced parallel implementations; and much more. Specific experimental results are presented for every application - as are detailed problem descriptions and easy-to-adapt examples. Genetic algorithms are already being incorporated into leading electronic design automation systems. Leverage their full power now - with Genetic Algorithms For VLSI Design, Layout, and Test Automation.
Author Biography
PINAKI MAZUMDER is Professor in the Department of Electrical Engineering and Computer Science at The University of Michigan, Ann Arbor. He has worked for over six years at AT&T Bell Laboratories (USA), NTT (Japan), and BEL (India). He has coauthored a book entitled Testing and Testable Design of High-Density Random-Access Memories and has published over 100 archival papers on VLSI testing, physical design automation, and high-speed circuit design.
ELIZABETH M. RUDNICK is Assistant Professor at the Center for Reliable and High-Performance Computing and the Department of Electrical and Computer Engineering, University of Illinois, Urbana. She has worked at Motorola, Sunrise Test Systems, and AMD, specializing in design verification, test generation, and electronic design automation.
Table of Contents
Preface |
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xi | |
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1 | (36) |
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Introduction to GA Terminology |
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3 | (2) |
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5 | (2) |
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The Steady-State Algorithm |
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7 | (2) |
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9 | (7) |
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9 | (1) |
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10 | (2) |
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12 | (1) |
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13 | (1) |
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14 | (2) |
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16 | (2) |
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GAs for VLSI Design, Layout, and Test Automation |
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18 | (19) |
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20 | (2) |
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22 | (4) |
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26 | (4) |
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Technology Mapping for FPGAs |
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30 | (2) |
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Automatic Test Generation |
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32 | (2) |
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34 | (3) |
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37 | (32) |
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38 | (8) |
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41 | (1) |
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Taxonomy of Partitioning Algorithms |
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42 | (4) |
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Circuit Partitioning by Genetic Algorithm |
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46 | (14) |
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Incorporation and Duplicate Check |
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52 | (1) |
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53 | (2) |
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Genetic Multiway Partitioning |
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55 | (1) |
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56 | (2) |
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58 | (2) |
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Hybrid Genetic Algorithm for Ratio-Cut Partitioning |
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60 | (7) |
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61 | (1) |
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Selection, Crossover, and Mutation |
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61 | (1) |
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62 | (2) |
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64 | (1) |
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Weighted DFS Reordering (WDFR) |
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64 | (1) |
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65 | (1) |
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65 | (1) |
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Comparison of GA with Other Methods |
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66 | (1) |
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67 | (2) |
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Standard Cell and Macro Cell Placement |
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69 | (38) |
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71 | (14) |
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72 | (4) |
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76 | (2) |
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Optimizing the Genetic Algorithm |
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78 | (2) |
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Comparison with Simulated Annealing |
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80 | (1) |
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81 | (4) |
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85 | (22) |
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87 | (3) |
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Application to Macro Cell Placement |
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90 | (8) |
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98 | (6) |
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Limitations and Enhancements |
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104 | (3) |
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107 | (33) |
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The Steiner Problem in a Graph |
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109 | (26) |
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110 | (1) |
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Description of the Algorithm |
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111 | (7) |
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118 | (3) |
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121 | (13) |
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134 | (1) |
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Macro Cell Global Routing |
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135 | (5) |
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Routing Phase I: Applying the GA for the SPG |
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135 | (1) |
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Routing Phase II: Minimizing Layout Area |
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136 | (1) |
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137 | (1) |
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138 | (2) |
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140 | (18) |
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141 | (2) |
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Circuit Segmentation and FPGA Mapping |
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143 | (7) |
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TLU-Based FPGA Architecture |
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143 | (3) |
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Mapping Using Circuit Segmentation |
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146 | (4) |
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Circuit Segmentation for Pseudo-Exhaustive Testing |
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150 | (1) |
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151 | (5) |
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Results for FPGA Technology Mapping |
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151 | (3) |
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Experimental Results of Segmentation for PET |
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154 | (2) |
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156 | (2) |
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Automatic Test Generation |
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158 | (69) |
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160 | (5) |
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Test Generation in a GA Framework |
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165 | (13) |
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167 | (1) |
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168 | (1) |
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168 | (3) |
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171 | (3) |
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Evaluation of GA Parameters |
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174 | (4) |
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Test Generation for Test Application Time Reduction |
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178 | (6) |
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Deterministic/Genetic Test Generator Hybrids |
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184 | (15) |
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186 | (4) |
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190 | (9) |
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Use of Finite State Machine Sequences |
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199 | (13) |
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201 | (5) |
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206 | (1) |
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Test Generation Procedure |
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207 | (3) |
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210 | (2) |
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Dynamic Test Sequence Compaction |
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212 | (12) |
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214 | (4) |
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218 | (6) |
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224 | (3) |
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227 | (25) |
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229 | (5) |
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Adding Delay Models to the Problem |
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232 | (2) |
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Application of Genetic Algorithms to Peak Power Estimation |
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234 | (1) |
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Estimation of Peak Single-Cycle and n-Cycle Powers |
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235 | (2) |
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Resolving the Problem of State Reachability |
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236 | (1) |
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Peak Sustainable Power Estimation |
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237 | (2) |
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239 | (10) |
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249 | (3) |
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252 | (43) |
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Wolverines: Standard Cell Placement on a Network of Workstations |
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254 | (26) |
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Standard Cell Placement Using the Genetic Algorithm |
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255 | (3) |
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Analysis of Serial Algorithm |
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258 | (1) |
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Distributed Placement Algorithm |
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259 | (5) |
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264 | (16) |
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280 | (1) |
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Parallel Genetic Algorithms for Automatic Test Generation |
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280 | (15) |
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281 | (3) |
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284 | (4) |
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288 | (5) |
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293 | (2) |
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295 | (10) |
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296 | (1) |
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297 | (1) |
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298 | (1) |
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298 | (2) |
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Genetic Algorithms vs. Conventional Algorithms |
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300 | (1) |
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301 | (4) |
Glossary |
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305 | (9) |
Bibliography |
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314 | (18) |
Index |
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332 | (4) |
About the Authors |
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336 | |
Excerpts
Preface This book describes how genetic algorithms (GAs)can be utilized for developing effcient computer-aided design (CAD)tools for performing VLSI design optimiza- tion,layout generation,and chip testing tasks.It is written primarily for practicing CAD engineers and academic researchers who want to apply GAs and analyze their performance in solving large VLSI/CAD optimization problems. Although GAs were developed over twenty-five years ago, not much research and experimental work have been done to ascertain their capabilities in solving complex and extremely large constrained combinatorial optimization problems that one generally encounters in designing VLSI/CAD tools. Unlike graph theoretic approaches, integer/linear programming, simulated annealing, and a host of other optimization techniques that have been quite successfully deployed as core problem solving methods in various VLSI/CAD tools, GAs are not yet as widely used. We hope that this book will motivate readers to widely apply GAs in developing VLSI/CAD tools. For this purpose, we have carefully selected a few important VLSI design automation problems with unique problem solving features, and we have shown how in each case, various aspects of the GA, namely its chromosome, crossover and mutation operators, etc., can be separately formulated to solve these problems. In order to estimate the e ffectiveness of GAs, we have compared their performance with conventional algorithms. While most of the solution techniques proposed in this book have been developed in an ad hoc and exploratory manner,the basic formulations of the GAs are, nevertheless, applicable to a range of related problems. However, further experimentation is needed to find better settings of GA parameters for each problem. If the empirical study is also combined with insightful mathematical modeling, then we strongly believe that the performance of the genetic-based tools can be further improved and real payoffs of the use of GAs in CAD tools can be demonstrated. The main objectives of this book are: to aggregate various genetic-based research work performed by the authors and their coresearchers at The University of Michigan, Ann Arbor, and the University of Illinois, Urbana,as well as by colleagues at the University of Iowa, Iowa City; to educate readers in the VLSI/CAD community about the merits of GAs by demonstrating some sample solution techniques; to motivate readers to develop improved techniques with appropriate mathematical formulations; and finally, to encourage readers working in other fields of science and engineering to explore the GA as a powerful method for solving problems in their areas of work. We have included sufficient introductory material to enable a reader who is not well-versed in GAs to know how to use them effectively. It is our sincere hope that in the future, GAs will prove to be a general-purpose heuristic method for solving a wider class of engineering and scientific problems. Another purpose of this book is to foster research work on the development of distributed CAD tools that run efficiently on a network of workstations. Originally, Prof.Mazumder's research group was intrigued by the intrinsic parallelism of GAs and the group embarked upon this research work with a view toward developing a suite of VLSI layout tools that can efficiently utilize the distributed resources of a network of workstations loosely connected through a local area network. With the availability of inexpensive personal computers and workstations that can be linked via an Ethernet type network, the CAD tool development environment has dramatically shifted from a single powerful uniprocessor to a cluster of networked desk-top computers. The main goal for developing this suite of distributed layout tools was to demonstrate that GAs are uniquely suited for running concurrently on a number of workstations without requiring much communication overhead. In the rece