Introduction to VLSI Circuits and Systems

by
Edition: CD
Format: Hardcover
Pub. Date: 2001-07-01
Publisher(s): Wiley
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Summary

Presents modern CMOS logic circuits, fabrication, and layout in a cohesive manner that links the material together with the system-level considerations. * Chapter on Verilog HDL allows for rapid start-up. * Illustrates the top-down design procedure used in modern VLSI chip design with an emphasis on variations in the HDL, logic, circuits and layout.

Table of Contents

Preface iv
Table of Contents
ix
An Overview of VLSI
1(14)
Complexity and Design
1(6)
Basic Concepts
7(4)
Plan of the Book
11(1)
General References
11(4)
Part 1 - Silicon Logic
Logic Design with MOSFETs
15(52)
Ideal Switches and Boolean Operations
15(5)
MOSFETs as Switches
20(8)
Basic Logic Gates in CMOS
28(12)
Complex Logic Gates in CMOS
40(15)
Transmission Gate Circuits
55(5)
Clocking and Dataflow Control
60(3)
Further Reading
63(1)
Problems
64(3)
Physical Structure of CMOS Integrated Circuits
67(48)
Integrated Circuit Layers
67(8)
MOSFETs
75(18)
CMOS Layers
93(3)
Designing FET Arrays
96(14)
References for Further Reading
110(1)
Problems
110(5)
Fabrication of CMOS Integrated Circuits
115(32)
Overview of Silicon Processing
115(4)
Material Growth and Deposition
119(7)
Lithography
126(6)
The CMOS Process Flow
132(8)
Design Rules
140(6)
Further Reading
146(1)
Elements of Physical Design
147(44)
Basic Concepts
147(3)
Layout of Basic Structures
150(17)
Cell Concepts
167(6)
FET Sizing and the Unit Transistor
173(7)
Physical Design of Logic Gates
180(4)
Design Hierarchies
184(3)
References for Further Reading
187(4)
Part 2 - The Logic-Electronics Interface
Electrical Characteristics of MOSFETs
191(46)
MOS Physics
191(7)
nFET Current-Voltage Equations
198(14)
The FET RC Model
212(11)
pFET Characteristics
223(6)
Modeling of Small MOSFETs
229(6)
References for Further Reading
235(1)
Problems
235(2)
Electronic Analysis of CMOS Logic Gates
237(56)
DC Characteristics of the CMOS Inverter
237(7)
Inverter Switching Characteristics
244(13)
Power Dissipation
257(3)
DC Characteristics: NAND and NOR Gates
260(6)
NAND and NOR Transient Response
266(6)
Analysis of Complex Logic Gates
272(4)
Gate Design for Transient Performance
276(5)
Transmission Gates and Pass Transistors
281(4)
Comments on SPICE Simulations
285(3)
References for Further Study
288(1)
Problems
288(5)
Designing High-Speed CMOS Logic Networks
293(46)
Gate Delays
293(10)
Driving Large Capacitive Loads
303(10)
Logical Effort
313(14)
BiCMOS Drivers
327(8)
Books for Further Reading
335(1)
Problems
336(3)
Advanced Techniques in CMOS Logic Circuits
339(32)
Mirror Circuits
339(3)
Pseudo-nMOS
342(2)
Tri-State Circuits
344(2)
Clocked CMOS
346(7)
Dynamic CMOS Logic Circuits
353(7)
Dual-Rail Logic Networks
360(6)
Additional Reading
366(1)
Problems
366(5)
Part 3 - The Design of VLSI Systems
System Specifications Using Verilog HDL
371(32)
Basic Concepts
371(2)
Structural Gate-Level Modeling
373(10)
Switch-Level Modeling
383(5)
Design Hierarchies
388(4)
Behavioral and RTL Modeling
392(7)
References
399(1)
Problems
400(3)
General VLSI System Components
403(40)
Multiplexors
403(8)
Binary Decoders
411(2)
Equality Detectors and Comparators
413(4)
Priority Encoder
417(3)
Shift and Rotation Operations
420(4)
Latches
424(7)
D Flip-Flop
431(5)
Registers
436(3)
The Role of Synthesis
439(1)
References for Further Study
440(1)
Problems
441(2)
Arithemetic Circuits in CMOS VLSI
443(40)
Bit Adder Circuits
443(8)
Ripple-Carry Adders
451(3)
Carry Look-Ahead Adders
454(13)
Other High-Speed Adders
467(4)
Multipliers
471(10)
Summary
481(1)
References
481(1)
Problems
481(2)
Memories and Programmable Logic
483(40)
The Static RAM
483(5)
SRAM Arrays
488(10)
Dynamic RAMs
498(8)
ROM Arrays
506(7)
Logic Arrays
513(6)
References
519(1)
Problems
519(4)
System-Level Physical Design
523(48)
Large-Scale Physical Design
523(2)
Interconnect Delay Modeling
525(11)
Crosstalk
536(6)
Interconnect Scaling
542(2)
Floorplanning and Routing
544(5)
Input and Output Circuits
549(9)
Power Distribution and Consumption
558(7)
Low-Power Design Considerations
565(2)
References for Further Study
567(1)
Problems
568(3)
VLSI Clocking and System Design
571(42)
Clocked Flip-flops
571(4)
CMOS Clocking Styles
575(14)
Pipelined Systems
589(5)
Clock Generation and Distribution
594(12)
System Design Considerations
606(5)
References for Advanced Reading
611(2)
Reliability and Testing of VLSI Circuits
613(24)
General Concepts
613(7)
CMOS Testing
620(7)
Test Generation Methods
627(9)
Summary
636(1)
References
636(1)
Index 637

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