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Summary
Table of Contents
Preface | p. xi |
Authors | p. xiii |
NoC-Based System-Level Design | |
NoC and System-Level Design | p. 3 |
Introduction to SoC Design | p. 3 |
System Model and Design Flow | p. 6 |
System Analysis with UML | p. 9 |
Architecture Design | p. 16 |
Platform-Based SoC Design | p. 21 |
Concept of the Platform | p. 21 |
Types of Platforms | p. 24 |
Processor-Centric Platform | p. 27 |
Application-Specific Platform | p. 29 |
Fully Programmable Platform | p. 30 |
Communication-Centric Platform | p. 30 |
Multiprocessor SoC and Network on Chip | p. 34 |
Concept of MPSoC | p. 34 |
MPSoC and NoC | p. 36 |
Low-Power SoC Design | p. 37 |
CMOS Circuit-Level Low-Power Design | p. 37 |
Architecture-Level Low-Power Design | p. 40 |
System-Level Low-Power Design | p. 41 |
Trends in Low-Power Design | p. 43 |
References | p. 45 |
System Design with Model of Computation | p. 47 |
System Models | p. 47 |
Types of Models | p. 48 |
Communication | p. 49 |
Behavior: Time and State Space | p. 49 |
Models of Computation | p. 52 |
Finite State Machine and Its Variants | p. 52 |
Petri Net | p. 54 |
Transaction-Level Modeling | p. 55 |
Dataflow Graph and Its Variants | p. 57 |
Process Algebra-Based Semantics | p. 61 |
Summary | p. 62 |
Validation and Verification | p. 64 |
Simulation | p. 65 |
Discrete-Event Simulation | p. 66 |
Cycle-Based Simulation | p. 66 |
Transaction-Level Simulation | p. 68 |
Formal Method | p. 69 |
References | p. 71 |
Hardware/Software Codesign | p. 73 |
Codesign | p. 73 |
Application Analysis | p. 77 |
Performance Index | p. 77 |
Task Graph: Sound Semantics for Application Analysis | p. 79 |
Implementing Task Graph in Unified Modeling Language (UML) | p. 83 |
Synthesis | p. 89 |
Partitioning and Resource Allocation | p. 89 |
Scheduling | p. 99 |
References | p. 99 |
Computation-Communication Partitioning | p. 101 |
Communication System: Current Trend | p. 101 |
Separation of Communication and Computation | p. 106 |
Communication-Centric SoC Design | p. 107 |
Overview | p. 107 |
OCP-IP: Socket Abstraction | p. 109 |
Communication Synthesis | p. 111 |
High-Level Communication System Design | p. 112 |
Communication Design Methods | p. 115 |
Network-Based Design | p. 123 |
References | p. 127 |
NoC-Based Real Chip Implementation | |
Network on Chip-Based SoC | p. 131 |
Network on Chip | p. 131 |
NoC for SoC Design | p. 131 |
Comparison of Bus-Based and NoC-Based SoC Design | p. 133 |
OSI Seven-Layer NoC Model | p. 134 |
An Example of NoC-Based SoC Design | p. 138 |
Architecture of NoC | p. 139 |
Basic NoC Design Issues | p. 139 |
Design of NoC Building Blocks | p. 142 |
High-Speed Signaling | p. 142 |
Queue and Buffer Design | p. 142 |
Switch Design | p. 144 |
Scheduler Design | p. 145 |
Practical Design of NoC | p. 147 |
Topology Selection | p. 147 |
Routing Scheme | p. 148 |
Switching Scheme | p. 148 |
Phit Size Determination | p. 149 |
SERDES Design | p. 151 |
Mesochronous Synchronizer | p. 151 |
References | p. 154 |
NoC Topology and Protocol Design | p. 157 |
Introduction | p. 157 |
Analysis Methodology | p. 159 |
Topology Pool and Target System | p. 159 |
NoC Traffic and Energy Models | p. 160 |
Energy Exploration | p. 162 |
Bus Topology | p. 162 |
Mesh Topology | p. 164 |
Star Topology | p. 166 |
Point-to-Point Topology | p. 166 |
Heterogeneous Topologies | p. 168 |
NoC Protocol Design | p. 168 |
Layered Architecture | p. 172 |
Physical Layer Protocol | p. 173 |
Data Link Layer Protocol | p. 175 |
Network Layer Protocol | p. 176 |
Transport Layer Protocol | p. 178 |
Multiple-Outstanding-Addressing | p. 179 |
Write with Acknowledge | p. 179 |
Burst Packet Transfer | p. 179 |
Enhanced Burst Packet Transfer | p. 181 |
Protocol Design with Finite State Machine Model | p. 182 |
Packet Design for NoC | p. 183 |
Summary | p. 187 |
References | p. 187 |
Low-Power Design for NoC | p. 189 |
Introduction | p. 189 |
Low-Power Signaling | p. 189 |
Channel Coding to Reduce the Switching Probability-[alpha] | p. 190 |
Wire Capacitance Reducing Techniques | p. 191 |
Low-Swing Signaling | p. 191 |
Driver Circuits | p. 191 |
Receiver Circuits | p. 191 |
Static and Dynamic Wires | p. 193 |
Optimal Voltage Swing | p. 193 |
Frequency and Voltage Scaling | p. 194 |
On-Chip Serialization | p. 194 |
Area and Energy-Consumption Variation Due to the OCS | p. 195 |
Optimal Serialization Ratio | p. 196 |
Low-Power Clocking | p. 197 |
Clock Distribution inside the NoC | p. 197 |
Synchronizers | p. 198 |
Low-Power Channel Coding | p. 200 |
SILENT Coding | p. 200 |
Performance Analysis of SILENT Coding | p. 203 |
SILENT Coding for Multimedia Applications | p. 205 |
Low-Power Switch | p. 206 |
Low-Power Technique for Switch Fabric | p. 206 |
Crossbar Partial Activation Technique | p. 206 |
Switch Scheduler | p. 207 |
Low-Power Scheduler: Mux-Tree-Based Round-Robin Scheduler | p. 208 |
Low-Power Network on Chip Protocol | p. 210 |
Protocol Definition | p. 210 |
Protocol Composition | p. 210 |
Low-Power Issues on the NoC Protocol | p. 211 |
Aligned Packet Formation | p. 211 |
Packet Switching versus Circuit Switching | p. 212 |
References | p. 213 |
Real Chip Implementation | p. 217 |
Introduction | p. 217 |
BONE Series | p. 217 |
BONE 1: Prototype of On-Chip Network (PROTON) | p. 217 |
Overall Architecture | p. 218 |
Packet Routing Scheme | p. 219 |
Off-Chip Connectivity | p. 221 |
BONE 2: Low-Power Network on Chip and Network in Package (Slim Spider) | p. 221 |
NoC Architecture | p. 222 |
Low-Power Techniques | p. 224 |
Design Methodology and Chip Implementation | p. 225 |
Networks in Package and Measurement | p. 226 |
BONE 2 Chip Summary | p. 229 |
BONE 3 (Intelligent Interconnect System) | p. 230 |
Supply-Voltage-Dependent Reference Voltage | p. 231 |
Self-Calibrating Phase Difference | p. 231 |
Adaptive-Link Bandwidth Control | p. 232 |
BONE 4 Flexible On-Chip Network (FONE) | p. 232 |
NoC Evaluation Platform | p. 232 |
NoC Run-Time Traffic-Monitoring System | p. 233 |
Case Study: Portable Multimedia System | p. 235 |
FONE Platform Summary | p. 239 |
BONE V1: Vision Application-1 | p. 239 |
Introduction | p. 239 |
Architecture and Operation | p. 239 |
Benefits of the MC-NoC | p. 243 |
Evaluation of the MC-NoC | p. 245 |
Industrial Implementations | p. 245 |
Intel's Tera-FLOP 80-Core NoC | p. 245 |
Key Enablers for Tera-FLOP on a Chip [18] | p. 246 |
NoC Architecture Overview [18] | p. 246 |
Double-Pumped Crossbar Router and Mesochronous Interface | p. 248 |
Fine-Grained Power Management | p. 248 |
Intel's Scalable Communication Architecture [22] | p. 249 |
Scalable Communication Core | p. 249 |
Prototype Architecture | p. 250 |
Control Plane (OCP-Bus) | p. 252 |
Data Plane (NoC) | p. 252 |
Data Flow and Reusability | p. 253 |
Academic Implementations | p. 253 |
FAUST (Flexible Architecture of Unified System for Telecom) | p. 253 |
RAW | p. 256 |
References | p. 258 |
BONE Protocol Specification | p. 261 |
Overview of BONE | p. 261 |
BONE Protocol | p. 262 |
Packet Format | p. 262 |
BONE Signals | p. 264 |
Master Network Interface (MNI) | p. 264 |
Up_Sampler (UPS) | p. 267 |
Switch (SW) | p. 268 |
Dn_Sampler (DNS) | p. 269 |
Slave Network Interface (SNI) | p. 270 |
Packet Transactions | p. 272 |
Timing Diagrams | p. 275 |
Basic Read Packet Transaction | p. 275 |
Basic Write Packet Transaction | p. 278 |
UPS/DNS Timing Diagram | p. 279 |
SW Timing Diagram | p. 280 |
Index | p. 283 |
Table of Contents provided by Ingram. All Rights Reserved. |
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