Reconfigurable Computing: Architectures, Tools and Applications : 7th International Symposium, ARC 2011, Belfast, UK, March 23-25, 2011, Proceedings
by Koch, Andreas; Krishnamurthy, Ram; Mcallister, John; Woods, Roger; El-Ghazawi, TarekFormat: Paperback
Pub. Date: 2011-05-03
Publisher(s): Springer-Verlag New York Inc
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Summary
This book constitutes the refereed proceedings of the 7th International Symposium on Reconfigurable Computing: Architectures, Tools and Applications, ARC 2011, held in Belfast, UK, in March 2011. The 40 revised papers presented, consisting of 24 full papers, 14 poster papers, and the abstracts of 2 plenary talks, were carefully reviewed and selected from 88 submissions. The topics covered are reconfigurable accelerators, design tools, reconfigurable processors, applications, device architecture, methodology and simulation, and system architecture.
Table of Contents
| Plenary Talks | |
| Reconfigurable Computing for High Performance Networking Applications | p. 1 |
| Biologically-Inspired Massively-Parallel Architectures: A Reconfigurable Neural Modelling Platform | p. 2 |
| Reconfigurable Accelerators I | |
| A Reconfigurable Audio Beamforming Multi-Core Processor | p. 3 |
| A Regular Expression Matching Circuit Based on a Decomposed Automaton | p. 16 |
| Design and Implementation of a Multi-Core Crypto-Processor for Software Defined Radios | p. 29 |
| Design Tools | |
| Application Specific Memory Access, Reuse and Reordering for SDRAM | p. 41 |
| Automatic Generation of FPGA-Specific Pipelined Accelerators | p. 53 |
| HLS Tools for FPGA: Faster Development with Better Performance | p. 67 |
| Posters 1 | |
| A (Fault-Tolerant)2 Scheduler for Real-Time Hw Tasks | p. 79 |
| A Compact Gaussian Randon Number Generator for Small Word Lengths | p. 88 |
| Accurate Floating Point Arithmetic through Hardware Error-Free Transformations | p. 94 |
| Active storage Networks for Acceleratinog K-Means Data Clustering | p. 102 |
| An FPGA Implementation for Texture Analysis Considering the Real-Time Requirements of Vision-Based Systems | p. 110 |
| CReAMS: An Embedded Multiprocessor Platform | p. 118 |
| Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Recofigurable Architecture | p. 125 |
| Reconfigurable Processors | |
| A Pipeline Interleaved Heterogeneous SIMD Soft Processor Array Architecture for MIMO-OFDM | p. 133 |
| Design Implementation, and Verification of an Adaptable Processor in Lava HDL | p. 145 |
| Towards an Adaptable Multiple-ISA Reconfigurable Processor | p. 157 |
| Applications | |
| FPGA-Based Cherenkov Ring Rcognition in Nuclear and Particle Physics Experiments | p. 169 |
| FPGA-Based Smith-Waterman Algorithm: Analysis and Novel design | p. 181 |
| Index to Constant Weight Codeword Converter | p. 193 |
| On-Chip Ego-Motion Estimation Based on Optical Flow | p. 206 |
| Device Architecture | |
| Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGAa | p. 218 |
| Dynamic VDD Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction | p. 230 |
| MEMS Interleaving Read Operation of a Holographic Memory for Optically Reconfigurable Gate Arrays | p. 242 |
| Posters 2 | |
| FaRM: Fast Reconfiguration Manager for Reducing Reconfiguration Time Overhead on FPGA | p. 253 |
| Feasibility Analysis of Reconfigurable Computing in Low-Power Wireless Sensor Applications | p. 261 |
| Hierarchical Optical Flow Estimation Architecture Using Color Cues | p. 269 |
| Magnetic Look-Up Table (MLUT) Featuring Radiation Hardness, High Performance and Low power | p. 275 |
| Reconfigurable Stream-Processing Architecture for Sparse Linear Solvers | p. 281 |
| The Krawczyk Algorithm: Rigorous Bounds for Linear Equation Solution on an FPGA | p. 287 |
| A Dynamic Reconfigurable CPLD Architecture for Structured ASIC Technology | p. 296 |
| Reconfigurable Accelerators II | |
| FPGA Accelerated Parallel Sparse Matrix Factorization for Circuit Simulations | p. 302 |
| FPGA Optimizations for a Pipelined Floating-Point Exponential Unit | p. 316 |
| NetStage/DPR: A Self-adaptable FPGA Platform for Application-Level Network Security | p. 328 |
| Methodology and Simulation | |
| A Correlation Power Analysis Attack against Tate Pairing on FPGA | p. 340 |
| From Plasma to BeeFarm: Design Experience of an FPGA-Based Multicore Prototype | p. 350 |
| System Architecture | |
| Architectural Support for Multithreading on Reconfigurable Hardware | p. 363 |
| High Performance Programmable FPGA Overlay for Digital Signal Processing | p. 375 |
| Secure Virtualization within a Multi-processor Soft-Core System-en-Chip Architecture | p. 385 |
| Author Index | p. 397 |
| Table of Contents provided by Ingram. All Rights Reserved. |
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